Overview

During the different manufacture steps of an integrated circuit (IC), the structured metallic connecting conductors are covered with an intermetallic dielectric layer or a passivation layer. During the depositing of these dielectric layers, the wafer is heated to several hundred degrees Celsius. The metallic conductors expand and the volume is greater than the volume at room temperature. During cooling to room temperature, high mechanical tensile stresses are built up in the metallic conductor, which are caused by the different thermal expansion coefficients of the metallization and the surrounding material. If these tensions are completely relieved, the volume difference δV will occur in the form of a void defect. For sensitive metallizations, void defects can grow in the conductors as well as below or above the vias. Void defects can cause complete failures for simple metallizations. For metallizations, which have shunt coatings of refractory metals, the void defects can lead to an increase of the electrical resistance and, together with other failure mechanisms such as electromigration or mechanical failures, to a shortened life span. Void defects induced by mechanical stress present a reliability problem for microelectronic chips for which aluminium- (Al) based alloys or Cu (copper) are/is used for the chip side connection and build-up process. In this document, a stress void test and the associated criteria are specified. It is applicable to aluminium (Al) or copper (Cu) metallization. This document is applicable for reliability testing as well as for qualification tests for semiconductor manufacturing methods. The responsible Committee is "Halbleiterbauelemente" ("Semiconductor devices") of the DKE (German Commission for Electrical, Electronic and Informational Technologies) at DIN and VDE.

Responsible national committee

DKE/K 631 - Halbleiterbauelemente