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EIA JESD 79F
DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
Edition
2010-02
EIA JESD 82
Definition of CDCV857 PLL Clock Driver for Registered DDR DIMM Applications
Edition
2000-07
EIA JESD 73-3
Standard for Description of 3867: 2.5 V, 10-Bit, 2-Port, DDR FET Switch
Edition
2001-11
EIA JESD 73-4
7Standard for Description of 3867: 2.5 V, Dual 5-Bit, 2-Port, DDR FET Switch
Edition
2001-11
EIA JESD 82-6A.01
Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL 2 Registered Buffer for 1U Stacked DDR DIMM Applications
Edition
2023-01
EIA JESD 82-13A.01
Definition of the SSTVN16859 2.5-2.6 V 13-Bit to 26-Bit SSTL 2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications
Edition
2023-02
EIA JESD 82-4B
Definition of the SSTV16859 2.5 V 13-Bit to 26-Bit SSTL 2 Registered Buffer for Stacked DDR DIMM Applications
Edition
2003-05
EIA JESD 82-3B
Definition of the SSTVN16857 2.5-2.6 V 14-Bit SSTL 2 Registered Buffer for PC1600, PC2100, PC2700, and PC3200 DDR DIMM Applications
Edition
2004-11
DIN 33903
Information and documentation - Romanization of Tamil
Edition
2016-02
DIN EN 60958-4-4
Digital audio interface - Part 4-4: Professional applications - Physical and electrical parameters (IEC 60958-4-4:2016); German version EN 60958-4-4:2016
Edition
2017-01