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JIS X 5001
Character structure on the transmission circuits and horizontal parity method
Edition
1982-02-28
EIA JESD 82-23.01
Definition of the SSTUA32S869 and SSTUA32D869 Registered Buffer with Parity for DDR2 RDIMM Applications
Edition
2023-01
EIA JESD 82-26.01
Definition of the SSTUB32868 Registered Buffer with Parity for 2R x4 DDR2 RDIMM Applications
Edition
2023-01
EIA JESD 82-12A.01
Definition of the SSTU32S869 and SSTU32D869 Registered Buffer with Parity for DDR2 RDIMM Applications
Edition
2023-01
EIA JESD 82-27.01
Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications
Edition
2023-03
EIA JESD 82-9B
Definition of the SSTU32865 Registered Buffer with Parity for 2R · 4 DDR2 RDIMM Applications
Edition
2007-05
EIA JESD 82-24.01
Definition of the SSTUB32865 28-bit 1:2 Registered Buffer with Parity for DDR2 RDIMM Applications
Edition
2023-01
EIA JESD 82-17.01
Definition of the SSTUA32S868 and SSTUA32D868 Registered Buffer with Parity for 2R×4 DDR2 RDIMM Applications
Edition
2023-01
EIA JESD 82-25.01
Definition of the SSTUB32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications
Edition
2023-01
IEEE 1890
IEEE Standard for Error Correction Coding of Flash Memory Using Low-Density Parity Check Codes
Edition
2018
