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EIA JESD 82-25.01
Definition of the SSTUB32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications
Edition
2023-01
EIA JESD 82-26.01
Definition of the SSTUB32868 Registered Buffer with Parity for 2R x4 DDR2 RDIMM Applications
Edition
2023-01
EIA JESD 82-27.01
Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications
Edition
2023-03
EIA JESD 82-29A.01
Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications
Edition
2022-09
IEEE 1890
IEEE Standard for Error Correction Coding of Flash Memory Using Low-Density Parity Check Codes
Edition
2018
ISO 1155
Information processing - Use of longitudinal parity to detect errors in information messages
Edition
1978-11
DIN EN 300163
Television systems - NICAM 728: Transmission of two-channel digital sound with terrestrial television systems B, G, H, I, K1 and L; English version EN 300163 V 1.2.1 (1998.03)
Edition
1998-10
DIN ETS 300215
Network Aspects (NA); Metropolitan Area Network (MAN); physical layer convergence procedure for 139,264 Mbit/s; English version ETS 300215:1992
Edition
1993-07
DIN ETS 300213
Network Aspects (NA); Metropolitan Area Network (MAN); physical layer convergence procedure for 2,048 Mbit/s; English version ETS 300213:1992
Edition
1993-07
DIN ETS 300214
Network Aspects (NA); Metropolitan Area Network (MAN); physical layer convergence procedure for 34,368 Mbit/s; English version ETS 300214:1992
Edition
1993-07
